144 research outputs found

    Asynchronous design of Networks-on-Chip

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    Current Trends in High-Level Synthesis of Asynchronous Circuits

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    Packetizing OCP Transactions in the MANGO Network-on-Chip

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    Clock domain crossing modules for OCP-style read/write interfaces

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    A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

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    Submitted on behalf of EDAA (http://www.edaa.com/)International audienceOn-chip networks for future system-on-chip designs need simple, high performance implementations. In order to promote system-level integrity, guaranteed services (GS) need to be provided. We propose a network-on-chip (NoC) router architecture to support this, and demonstrate with a CMOS standard cell design. Our implementation is based on clockless circuit techniques, and thus inherently supports a modular, GALS-oriented design flow. Our router exploits virtual channels to provide connection-oriented GS, as well as connection-less best-effort (BE) routing. The architecture is highly flexible, in that support for different types of BE routing and GS arbitration can be easily plugged into the router

    A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip

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    A low-power asynchronous data-path for a FIR filter bank

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    A multicore processor for time-critical applications

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    Asynchronous circuit design - A tutorial

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    High-level synthesis for reduction of WCET in real-time systems

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